As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
The intrinsic complexity of most protocol speci cations in particular, and of asynchronous systems in general, lead us to study combinations of static analysis with classical model...
Marius Bozga, Jean-Claude Fernandez, Lucian Ghirvu
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
This paper describes a model-based analysis of errors in expert use of graphical user interfaces. Two mechanisms, speed-accuracy tradeoffs and attention failures, were simulated b...
Program analysis and optimizationcan be speeded upthrough the use of the dependence flow graph (DFG), a representation of program dependences which generalizes def-use chains and...