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CODES
2001
IEEE
15 years 10 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
IWMM
2000
Springer
122views Hardware» more  IWMM 2000»
15 years 10 months ago
Concurrent Garbage Collection Using Program Slices on Multithreaded Processors
We investigate reference counting in the context of a multithreaded architecture by exploiting two observations: (1) reference-counting can be performed by a transformed program s...
Manoj Plakal, Charles N. Fischer
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
15 years 10 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
ISLPED
1995
ACM
108views Hardware» more  ISLPED 1995»
15 years 10 months ago
Electroid-oriented adiabatic switching circuits
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
David J. Frank, Paul M. Solomon
PLDI
1995
ACM
15 years 10 months ago
Storage Assignment to Decrease Code Size
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...