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ICASSP
2011
IEEE
14 years 10 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan
AINA
2010
IEEE
14 years 10 months ago
A Novel Cross Layer Intrusion Detection System in MANET
— Intrusion detection System forms a vital component of internet security. To keep pace with the growing trends, there is a critical need to replace single layer detection techno...
Rakesh Shrestha, Kyong-Heon Han, Dong-You Choi, Se...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
16 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
TACAS
2012
Springer
277views Algorithms» more  TACAS 2012»
14 years 2 months ago
Proving Reachability Using FShell - (Competition Contribution)
FShell is an automated white-box test-input generator for C programs, computing test data with respect to user-specified code coverage criteria. The pillars of FShell are the decl...
Andreas Holzer, Daniel Kroening, Christian Schallh...