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CASES
2009
ACM
16 years 1 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
ICASSP
2008
IEEE
16 years 1 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
16 years 1 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
NOCS
2007
IEEE
16 years 1 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
WISE
2007
Springer
16 years 1 months ago
Building the Presentation-Tier of Rich Web Applications with Hierarchical Components
Nowadays information systems are increasingly distributed and deployed within the Internet platform. Without any doubt, the World Wide Web represents the de facto standard platform...
Reda Kadri, Chouki Tibermacine, Vincent Le Gloahec