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ATS
2003
IEEE
98views Hardware» more  ATS 2003»
16 years 22 days ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
16 years 21 days ago
A Proposal for Transaction-Level Verification with Component Wrapper Language
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Koji Ara, Kei Suzuki
190
Voted
MEMOCODE
2003
IEEE
16 years 21 days ago
Optimizations for Faster Execution of Esterel Programs
Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation ...
Dumitru Potop-Butucaru, Robert de Simone
ITC
1999
IEEE
118views Hardware» more  ITC 1999»
15 years 11 months ago
Logic BIST for large industrial designs: real issues and case studies
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
Graham Hetherington, Tony Fryars, Nagesh Tamarapal...
RSP
1998
IEEE
126views Control Systems» more  RSP 1998»
15 years 11 months ago
Testing Prototypes Validity to Enhance Code Reuse
The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newl...
Didier Buchs, A. Diagne, Fabrice Kordon