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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 11 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ISCAPDCS
2007
15 years 8 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
UAIS
2008
104views more  UAIS 2008»
15 years 6 months ago
A knowledge-based sign synthesis architecture
This paper presents the modules that comprise a knowledge-based sign synthesis architecture for Greek sign language (GSL). Such systems combine natural language (NL) knowledge, mac...
Stavroula-Evita Fotinea, Eleni Efthimiou, George C...
COMCOM
2002
120views more  COMCOM 2002»
15 years 6 months ago
The Cyclone Server Architecture: streamlining delivery of popular content
Abstract-We propose a new webserver architecture optimized for delivery of large, popular files. Delivery of such files currently pose a scalability problem for conventional conten...
Stanislav Rost, John W. Byers, Azer Bestavros
IPPS
2010
IEEE
15 years 4 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...