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TVLSI
2010
15 years 1 months ago
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
Hamed F. Dadgour, Kaustav Banerjee
SIGSOFT
2001
ACM
16 years 7 months ago
An architecture for flexible, evolvable process-driven user-guidance environments
Complex toolsets can be difficult to use. User interfaces can help by guiding users through the alternative choices that might be possible at any given time, but this tends to loc...
Timothy J. Sliski, Matthew P. Billmers, Lori A. Cl...
MOBISYS
2007
ACM
16 years 6 months ago
A time-and-value centric provenance model and architecture for medical event streams
Provenance becomes a critical requirement for healthcare IT infrastructures, especially when pervasive biomedical sensors act as a source of raw medical streams for large-scale, a...
Min Wang, Marion Blount, John Davis, Archan Misra,...
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
16 years 2 days ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 11 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...