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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
16 years 18 hour ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
ASPLOS
2000
ACM
15 years 11 months ago
Architecture and design of AlphaServer GS320
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer G...
Kourosh Gharachorloo, Madhu Sharma, Simon Steely, ...
SIGGRAPH
1998
ACM
15 years 11 months ago
Recovering Photometric Properties of Architectural Scenes from Photographs
In this paper, we present a new approach to producing photorealistic computer renderings of real architectural scenes under novel lighting conditions, such as at different times o...
Yizhou Yu, Jitendra Malik
LCTRTS
2010
Springer
16 years 1 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...