Sciweavers

5799 search results - page 420 / 1160
» Patterns Generate Architectures
Sort
View
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
DSN
2005
IEEE
15 years 8 months ago
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors an...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ODRL
2004
15 years 8 months ago
A Pervasive Application Rights Management Architecture (PARMA) based on ODRL
Software license management is currently expanding from its traditional desktop environment into the mobile application space, but software vendors are still applying old licensing...
Dominik Dahlem, Ivana Dusparic, Jim Dowling
ISCAPDCS
2003
15 years 8 months ago
Dynamic Simultaneous Multithreaded Architecture
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
Daniel Ortiz Arroyo, Ben Lee
JCP
2008
87views more  JCP 2008»
15 years 6 months ago
VLSI Architecture of a Cellular Automata based One-Way Function
In this paper, a technique to generate expander graphs using Cellular Automata (CA) has been presented. The special class of CA, known as the Two Predecessor Single Attractor Cellu...
Debdeep Mukhopadhyay, Pallavi Joshi, Dipanwita Roy...