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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 12 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
15 years 12 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
BROADNETS
2005
IEEE
15 years 11 months ago
Modeling and performance evaluation of ISCSI storage area networks
Abstract— This paper provides a concise modeling and performance evaluation of the iSCSI storage area network (SAN) architecture and protocol. SANs play a key role in business co...
Christoph M. Gauger, Martin Köhn, Sebastian G...
MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
15 years 11 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
SENSYS
2005
ACM
15 years 11 months ago
Data collection, storage, and retrieval with an underwater sensor network
In this paper we present a novel platform for underwater sensor networks to be used for long-term monitoring of coral reefs and fisheries. The sensor network consists of static a...
Iuliu Vasilescu, Keith Kotay, Daniela Rus, Matthew...