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ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
16 years 3 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
FSTTCS
2007
Springer
16 years 10 days ago
Covering Graphs with Few Complete Bipartite Subgraphs
We consider computational problems on covering graphs with bicliques (complete bipartite subgraphs). Given a graph and an integer k, the biclique cover problem asks whether the edg...
Herbert Fleischner, Egbert Mujuni, Daniël Pau...
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 10 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
HIPEAC
2009
Springer
16 years 29 days ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
CASES
2006
ACM
16 years 4 days ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh