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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 10 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
EVOW
2006
Springer
15 years 10 months ago
Artificial Life Models in Lung CTs
A new method for the analysis of 3D medical images is introduced. The algorithm is based on Biological Models of ants known as Artificial Life models. Test images (lung Computed To...
Sorin Cristian Cheran, Gianfranco Gargano
AMAST
2008
Springer
15 years 8 months ago
A Declarative Debugger for Maude
Abstract. Declarative debugging has been applied to many declarative programming paradigms; in this paper, a declarative debugger for rewriting logic specifications, embodied in th...
Adrián Riesco, Alberto Verdejo, Narciso Mar...
AAAI
2010
15 years 8 months ago
Parallel Depth First Proof Number Search
The depth first proof number search (df-pn) is an effective and popular algorithm for solving and-or tree problems by using proof and disproof numbers. This paper presents a simpl...
Tomoyuki Kaneko
DAGSTUHL
2007
15 years 8 months ago
Matrix Analytic Methods in Branching processes
We examine the question of solving the extinction probability of a particular class of continuous-time multi-type branching processes, named Markovian binary trees (MBT). The exti...
Sophie Hautphenne, Guy Latouche, Marie-Ange Remich...