5640 search results - page 749 / 1128 » Parallelizing the Data Cube |
156
Voted
IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
165
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HIPC
1999
Springer
15 years 11 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
172
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SIGMETRICS
1992
ACM
15 years 10 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
157
Voted
CLUSTER
2004
IEEE
15 years 10 months ago
2004
IEEE
Cluster computing environments built from commodity hardware have provided a cost-effective solution for many scientific and high-performance applications. Likewise, middleware te...
195
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DAC
2008
ACM
15 years 8 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...