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IPPS
1999
IEEE
15 years 11 months ago
The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks
We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchica...
Chi-Hsiang Yeh, Behrooz Parhami, Emmanouel A. Varv...
EUROPAR
1999
Springer
15 years 11 months ago
I/O-Conscious Tiling for Disk-Resident Data Sets
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ICS
1999
Tsinghua U.
15 years 11 months ago
Adapting cache line size to application behavior
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
HCW
1998
IEEE
15 years 11 months ago
Modular Heterogeneous System Development: A Critical Analysis of Java
Java supports heterogeneous applications by transforming a heterogeneous network of machines into a homogeneous network of Java virtual machines. This abstracts over many of the c...
Gul Agha, Mark Astley, Jamil A. Sheikh, Carlos A. ...
IPPS
1998
IEEE
15 years 11 months ago
A Mapping Methodology for Designing Software Task Pipelines for Embedded Signal Processing
Abstract. In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Pr...
Myungho Lee, Wenheng Liu, Viktor K. Prasanna