7092 search results - page 979 / 1419 » Parallelizing constraint programs |
180
Voted
ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
183
Voted
PDP
2009
IEEE
16 years 1 months ago
2009
IEEE
Existing approaches for modelling the Internet delay space predict end-to-end delays between two arbitrary hosts as static values. Further, they do not capture the characteristics...
189
Voted
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
191
Voted
HAPTICS
2009
IEEE
16 years 1 months ago
2009
IEEE
In this paper, we present the design of a new fMRI compatible haptic interface with 3DOFs, based on electrical DC actuation, for the study of brain mechanisms of human motor contr...
156
click to vote
IPPS
2009
IEEE
16 years 1 months ago
2009
IEEE
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximi...