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» Parallelism through Digital Circuit Design
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ET
2010
113views more  ET 2010»
15 years 3 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
TCAD
2002
146views more  TCAD 2002»
15 years 5 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
TC
1998
15 years 5 months ago
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
Alejandro F. González, Pinaki Mazumder
SBCCI
2004
ACM
134views VLSI» more  SBCCI 2004»
15 years 11 months ago
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage s...
Gabriella Trucco, Giorgio Boselli, Valentino Liber...
CCS
2011
ACM
14 years 5 months ago
VMCrypt: modular software architecture for scalable secure computation
Garbled circuits play a key role in secure computation. Unlike previous work, which focused mainly on efficiency and automation aspects of secure computation, in this paper we foc...
Lior Malka