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PATMOS
2004
Springer
16 years 3 days ago
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
15 years 7 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
SP
2002
IEEE
147views Security Privacy» more  SP 2002»
15 years 6 months ago
CX: A scalable, robust network for parallel computing
CX, a network-based computational exchange, is presented. The system's design integrates variations of ideas from other researchers, such as work stealing, non-blocking tasks...
Peter R. Cappello, Dimitros Mourloukos
171
Voted
IPPS
1998
IEEE
15 years 11 months ago
Implementing Parallelism in Random Discrete Event-Driven Simulation
Abstract. The inherently sequential nature of random discrete eventdriven simulation has made parallel and distributed processing di cult. This paper presents a method of applying ...
Marc Bumble, Lee D. Coraor
ENTCS
2002
65views more  ENTCS 2002»
15 years 6 months ago
Superposition: Composition vs refinement of non-deterministic action-based systems
We show that the traditional notion of superposition as used for supporting parallel program design can subsume both composition and refinement relationships when non-deterministi...
Antónia Lopes, José Luiz Fiadeiro