Sciweavers

3656 search results - page 646 / 732
» Parallel programming in Split-C
Sort
View
IPPS
2010
IEEE
15 years 4 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
CF
2009
ACM
16 years 21 days ago
Wave field synthesis for 3D audio: architectural prospectives
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, G...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
15 years 10 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
HPDC
1997
IEEE
15 years 10 months ago
A Secure Communications Infrastructure for High-Performance Distributed Computing
We describe a software infrastructure designed to support the development of applications that use high-speed networks to connect geographically distributed supercomputers, databa...
Ian T. Foster, Nicholas T. Karonis, Carl Kesselman...
EUROPAR
2010
Springer
15 years 6 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...