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ASPLOS
1996
ACM
15 years 10 months ago
An Integrated Compile-Time/Run-Time Software Distributed Shared Memory System
On a distributed memory machine, hand-coded message passing leads to the most efficient execution, but it is difficult to use. Parallelizing compilers can approach the performance...
Sandhya Dwarkadas, Alan L. Cox, Willy Zwaenepoel
COORDINATION
2009
Springer
16 years 7 months ago
High-Performance Transactional Event Processing
This paper presents a transactional framework for low-latency, high-performance, concurrent event processing in Java. At the heart of our framework lies Reflexes, a restricted prog...
Antonio Cunei, Rachid Guerraoui, Jesper Honig Spri...
CAV
2009
Springer
134views Hardware» more  CAV 2009»
16 years 7 months ago
Predecessor Sets of Dynamic Pushdown Networks with Tree-Regular Constraints
Abstract. Dynamic Pushdown Networks (DPNs) are a model for parallel programs with (recursive) procedures and process creation. The goal of this paper is to develop generic techniqu...
Alexander Wenner, Markus Müller-Olm, Peter La...
HPCA
2003
IEEE
16 years 7 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
RECOMB
2001
Springer
16 years 7 months ago
Predicting the beta-helix fold from protein sequence data
A method is presented that uses b-strand interactions to predict the parallel right-handed b-helix super-secondary structural motif in protein sequences. A program called BetaWrap...
Phil Bradley, Lenore Cowen, Matthew Menke, Jonatha...