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IPPS
2006
IEEE
16 years 23 days ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
16 years 21 days ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciď¬...
Robert L. Bocchino Jr., Vikram S. Adve
IPPS
2005
IEEE
16 years 10 days ago
COTS Clusters vs. the Earth Simulator: An Application Study Using IMPACT-3D
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
Daniel G. Chavarría-Miranda, Guohua Jin, Jo...
CP
2005
Springer
16 years 8 days ago
Boosting Distributed Constraint Satisfaction
Abstract Competition and cooperation can boost the performance of a combinatorial search process. Both can be implemented with a portfolio of algorithms which run in parallel, give...
Georg Ringwelski, Youssef Hamadi
173
Voted
EGC
2005
Springer
16 years 8 days ago
Transparent Fault Tolerance for Grid Applications
A major challenge facing grid applications is the appropriate handling of failures. In this paper we address the problem of making parallel Java applications based on Remote Method...
Pawel Garbacki, Bartosz Biskupski, Henri E. Bal