3656 search results - page 415 / 732 » Parallel programming in Split-C |
173
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PPOPP
2009
ACM
16 years 7 months ago
2009
ACM
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of ...
178
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
190
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
174
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HPCA
2002
IEEE
16 years 7 months ago
2002
IEEE
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
154
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IISWC
2009
IEEE
16 years 1 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...