104 search results - page 18 / 21 » Parallel processor scheduling with delay constraints |
157
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IEEEPACT
2002
IEEE
15 years 10 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
144
Voted
EURODAC
1994
IEEE
15 years 10 months ago
1994
IEEE
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
189
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RSP
2006
IEEE
15 years 11 months ago
2006
IEEE
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
147
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MICRO
1996
IEEE
15 years 10 months ago
1996
IEEE
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
169
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ICPP
1991
IEEE
15 years 9 months ago
1991
IEEE
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...