360 search results - page 17 / 72 » Parallel processing flow models on desktop hardware |
163
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FCCM
2006
IEEE
15 years 12 months ago
2006
IEEE
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
159
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
159
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3DPVT
2006
IEEE
15 years 12 months ago
2006
IEEE
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
156
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IPPS
2007
IEEE
16 years 5 days ago
2007
IEEE
DSP applications can be suitably represented using Process Network Models. This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum arch...
143
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ICASSP
2011
IEEE
14 years 9 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...