16159 search results - page 2828 / 3232 » Parallel computing with CUDA |
151
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...
230
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
165
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
152
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the outpu...
177
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...