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» Parallel and Distributed VHDL Simulation
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143
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HICSS
1996
IEEE
102views Biometrics» more  HICSS 1996»
15 years 10 months ago
Evaluation of Parallel Logic Simulation Using DVSIM
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
Gerd Meister
90
Voted
IPPS
2000
IEEE
15 years 10 months ago
Hardware Support for Simulated Annealing and Tabu Search
Reinhard Schneider, Reinhold Weiss