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HPDC
2006
IEEE
16 years 11 days ago
On the Harmfulness of Redundant Batch Requests
Most parallel computing resources are controlled by batch schedulers that place requests for computation in a queue until access to compute nodes is granted. Queue waiting times a...
Henri Casanova
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
15 years 10 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
JPDC
2006
120views more  JPDC 2006»
15 years 6 months ago
HeteroMPI: Towards a message-passing library for heterogeneous networks of computers
The paper presents Heterogeneous MPI (HeteroMPI), an extension of MPI for programming high-performance computations on heterogeneous networks of computers. It allows the applicati...
Alexey L. Lastovetsky, Ravi Reddy
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
15 years 11 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
EUROMICRO
2004
IEEE
15 years 10 months ago
Towards Predicting Real-Time Properties of a Component Assembly
This paper addresses the prediction of timing properties of a component-based application already during the composition phase. At this stage, it is of vital importance to guarant...
Egor Bondarev, Peter H. N. de With, Michel R. V. C...