5588 search results - page 506 / 1118 » Parallel Implementation of Bags |
173
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ICPP
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper we present a solution for efficient porting of sequential C++ applications on the Cell B.E. processor. We present our step-by-step approach, focusing on its general...
171
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ICPP
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper, a novel packet classification scheme optimized for multi-core network processors is proposed. The algorithm, Explicit Cuttings (ExpCuts), adopts a hierarchical spac...
175
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IEEECIT
2007
IEEE
16 years 1 months ago
2007
IEEE
Instruction window is a key component which extracts Instruction Level Parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor pe...
202
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IPPS
2007
IEEE
16 years 1 months ago
2007
IEEE
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
183
Voted
IPPS
2007
IEEE
16 years 1 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...