Sciweavers

5588 search results - page 480 / 1118
» Parallel Implementation of Bags
Sort
View
ARC
2009
Springer
142views Hardware» more  ARC 2009»
16 years 1 months ago
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
Abstract. This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF(p). We use this processor to compare a new algorit...
Brian Baldwin, Richard Moloney, Andrew Byrne, Gary...
INTENSIVE
2009
IEEE
16 years 1 months ago
Accelerating K-Means on the Graphics Processor via CUDA
In this paper an optimized k-means implementation on the graphics processing unit (GPU) is presented. NVIDIA’s Compute Unified Device Architecture (CUDA), available from the G8...
Mario Zechner, Michael Granitzer
ITNG
2007
IEEE
16 years 1 months ago
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
Hongyan Yang, Sotirios G. Ziavras, Jie Hu
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
16 years 27 days ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
CCGRID
2006
IEEE
16 years 27 days ago
DotGrid: A .NET-based Infrastructure for Global Grid Computing
Recently, Grid infrastructures have provided wide integrated use of resources. DotGrid intends to introduce required Grid services and toolkits that are implemented as a layer wra...
Alireza Poshtkohi, Ali Haj Abutalebi, Leila Mahmou...