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ASAP
2011
IEEE
247views Hardware» more  ASAP 2011»
14 years 6 months ago
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
Guohui Wang, Yang Sun, Joseph R. Cavallaro, Yuanbi...
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
16 years 26 days ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
GRID
2005
Springer
16 years 3 days ago
Highly latency tolerant Gaussian elimination
Large latencies over WAN will remain an obstacle to running communication intensive parallel applications on Grid environments. This paper takes one of such applications, Gaussian...
Toshio Endo, Kenjiro Taura
ICCCN
2008
IEEE
16 years 1 months ago
Instrumentation and Analysis of MPI Queue Times on the SeaStar High-Performance Network
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...
Ron Brightwell, Kevin T. Pedretti, Kurt B. Ferreir...
IPPS
2006
IEEE
16 years 18 days ago
Dedicated module access in dynamically reconfigurable systems
Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) du...
Jens Hagemeyer, Boris Kettelhoit, Mario Porrmann