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MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
15 years 4 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
IJCAI
1989
15 years 7 months ago
Neural Computing on a One Dimensional SIMD Array
Parallel processors offer a very attractive mechanism for the implementation of large neural networks. Problems in the usage of parallel processing in neural computing involve the...
Stephen S. Wilson
PODC
2004
ACM
16 years 15 hour ago
Compact routing on euclidian metrics
We consider the problem of designing a compact communication network that supports efficient routing in an Euclidean plane. Our network design and routing scheme achieves 1+ stret...
Ittai Abraham, Dahlia Malkhi
EUROPAR
2009
Springer
16 years 1 months ago
PSINS: An Open Source Event Tracer and Execution Simulator for MPI Applications
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...
Mustafa M. Tikir, Michael Laurenzano, Laura Carrin...
ISSAC
2007
Springer
91views Mathematics» more  ISSAC 2007»
16 years 22 days ago
Generation and optimisation of code using coxeter lattice paths
Supercomputing applications usually involve the repeated parallel application of discretized differential operators. Difficulties arise with higher-order discretizations of opera...
Thomas J. Ashby, Anthony D. Kennedy, Stephen M. Wa...