1295 search results - page 176 / 259 » Palimpsests of Time and Place |
156
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ITC
1997
IEEE
15 years 10 months ago
1997
IEEE
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
148
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MICRO
1997
IEEE
15 years 10 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
132
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SIGGRAPH
1997
ACM
15 years 10 months ago
1997
ACM
Virtual Reality (VR) has generated much excitement but little formal proof that it is useful. Because VR interfaces are difficult and expensive to build, the computer graphics co...
197
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JSSPP
1997
Springer
1997
Springer
An Experimental Evaluation of Processor Pool-Based Scheduling for Shared-Memory NUMA Multiprocessors
15 years 10 months ago
In this paper we describe the design, implementation and experimental evaluation of a technique for operating system schedulers called processor pool-based scheduling [51]. Our tec...
149
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CF
2007
ACM
15 years 10 months ago
2007
ACM
The transition to multithreaded, multi-core designs places a greater responsibility on programmers and software for improving performance; thread-level parallelism (TLP) will be i...