230 search results - page 20 / 46 » PPM Reduction on Embedded Memories in System on Chip |
142
click to vote
ACSAC
2008
IEEE
16 years 16 days ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
160
click to vote
CASES
2008
ACM
15 years 8 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
177
click to vote
TCAD
2010
15 years 23 days ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
159
click to vote
DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
144
click to vote
SIES
2008
IEEE
16 years 13 days ago
2008
IEEE
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...