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ISPASS
2007
IEEE
16 years 29 days ago
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
CF
2006
ACM
16 years 20 days ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
IUI
2006
ACM
16 years 19 days ago
Automatically classifying emails into activities
Email-based activity management systems promise to give users better tools for managing increasing volumes of email, by organizing email according to a user’s activities. Curren...
Mark Dredze, Tessa A. Lau, Nicholas Kushmerick
CGO
2005
IEEE
16 years 9 days ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
EDBTW
2004
Springer
16 years 2 days ago
P2PR-Tree: An R-Tree-Based Spatial Index for Peer-to-Peer Environments
Abstract. The unprecedented growth and increased importance of geographically distributed spatial data has created a strong need for efficient sharing of such data. Interestingly, ...
Anirban Mondal, Yi Lifu, Masaru Kitsuregawa