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» Optimizing the Use of High Performance Software Libraries
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CODES
2004
IEEE
15 years 10 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
HPCA
2006
IEEE
16 years 7 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
TIT
1998
81views more  TIT 1998»
15 years 6 months ago
Fast Iterative Coding Techniques for Feedback Channels
Abstract—A class of capacity-achieving, low-complexity, highreliability, variable-rate coding schemes is developed for communication over discrete memoryless channels with noisel...
James M. Ooi, Gregory W. Wornell
LCN
2006
IEEE
16 years 21 days ago
Minimizing Cache Misses in an Event-driven Network Server: A Case Study of TUX
We analyze the performance of CPU-bound network servers and demonstrate experimentally that the degradation in the performance of these servers under highconcurrency workloads is ...
Sapan Bhatia, Charles Consel, Julia L. Lawall
SERP
2003
15 years 8 months ago
Reliability Modeling Using UML
System reliability has become an increasingly important benchmark in measuring service continuity. As part of many service level agreements, system performance is gauged by how lo...
Chokchai Leangsuksun, Hertong Song, Lixin Shen