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MICRO
2005
IEEE
125views Hardware» more  MICRO 2005»
15 years 12 months ago
Improving Region Selection in Dynamic Optimization Systems
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...
David Hiniker, Kim M. Hazelwood, Michael D. Smith
CASES
2003
ACM
15 years 11 months ago
Vectorizing for a SIMdD DSP architecture
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
Dorit Naishlos, Marina Biberstein, Shay Ben-David,...
TC
2010
15 years 4 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
SC
2009
ACM
16 years 1 months ago
A case for integrated processor-cache partitioning in chip multiprocessors
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishr...
CODES
2005
IEEE
15 years 12 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra