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CGO
2006
IEEE
16 years 6 days ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
IPPS
2003
IEEE
15 years 11 months ago
Optimizing Synchronization Operations for Remote Memory Communication Systems
Synchronization operations, such as fence and locking, are used in many parallel operations accessing shared memory. However, a process which is blocked waiting for a fence operat...
Darius Buntinas, Amina Saify, Dhabaleswar K. Panda...
IPPS
2007
IEEE
16 years 13 days ago
An Implementation and Evaluation of Client-Side File Caching for MPI-IO
Client-side file caching has long been recognized as a file system enhancement to reduce the amount of data transfer between application processes and I/O servers. However, cach...
Wei-keng Liao, Avery Ching, Kenin Coloma, Alok N. ...
HPCA
2004
IEEE
16 years 6 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...
CASES
2005
ACM
15 years 8 months ago
Micro embedded monitoring for security in application specific instruction-set processors
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad ...