1990 search results - page 101 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
160
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JSA
2000
15 years 6 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
197
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CGO
2003
IEEE
15 years 11 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
162
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ICDCS
2006
IEEE
16 years 12 days ago
2006
IEEE
The inability to perform optimizations based on application-specific information presents a hurdle to the deployment of pervasive LAN file systems across WAN environments. This pa...
154
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ICPP
2005
IEEE
15 years 12 months ago
2005
IEEE
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
172
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CASES
2007
ACM
15 years 10 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...