2048 search results - page 48 / 410 » Optimizing pipelines for power and performance |
138
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ITNG
2007
IEEE
16 years 12 days ago
2007
IEEE
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
190
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CSREAESA
2004
15 years 7 months ago
2004
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
182
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CC
2008
Springer
15 years 8 months ago
2008
Springer
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
165
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WCNC
2010
IEEE
15 years 10 months ago
2010
IEEE
—We study the problem of optimizing the symbol error probability (SEP) performance of cluster-based cooperative wireless sensor networks (WSNs). It is shown in the literature tha...
165
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GLVLSI
1998
IEEE
15 years 10 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...