2048 search results - page 273 / 410 » Optimizing pipelines for power and performance |
181
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INFOCOM
2005
IEEE
15 years 12 months ago
2005
IEEE
— We consider a scenario where a wireless sensor network is formed by randomly deploying n sensors to measure some spatial function over a field, with the objective of computing...
188
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
169
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
174
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ISCA
2008
IEEE
16 years 24 days ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
312
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ISCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...