2048 search results - page 211 / 410 » Optimizing pipelines for power and performance |
182
click to vote
PLDI
2005
ACM
16 years 3 days ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
176
click to vote
HPCA
2000
IEEE
15 years 11 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
156
click to vote
MICRO
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
242
click to vote
CVPR
2012
IEEE
13 years 9 months ago
2012
IEEE
In this paper we examine the effect of receptive field designs on classification accuracy in the commonly adopted pipeline of image classification. While existing algorithms us...
176
click to vote
ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...