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» Optimizing pipelines for power and performance
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ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
ISLPED
2009
ACM
178views Hardware» more  ISLPED 2009»
16 years 1 months ago
Power management in energy harvesting embedded systems with discrete service levels
Power management has been a critical issue in the design of embedded systems due to the limited power supply. To prolong the lifetime, energy minimization has been studied under p...
Clemens Moser, Jian-Jia Chen, Lothar Thiele
IPPS
2005
IEEE
16 years 2 days ago
Power and Energy Profiling of Scientific Applications on Distributed Systems
Power consumption is a troublesome design constraint for emergent systems such as IBM’s BlueGene /L. If current trends continue, future petaflop systems will require 100 megawat...
Xizhou Feng, Rong Ge, Kirk W. Cameron
IEEEPACT
2006
IEEE
16 years 16 days ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
IISWC
2006
IEEE
16 years 16 days ago
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks
Many embedded real world applications are intellectual property, and vendors hesitate to share these proprietary applications with computer architects and designers. This poses a ...
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., L...