2048 search results - page 118 / 410 » Optimizing pipelines for power and performance |
136
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
131
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ARITH
2003
IEEE
15 years 11 months ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
172
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CASES
2006
ACM
15 years 10 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
189
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TIT
2002
15 years 6 months ago
2002
We consider direct sequence code division multiple access (DS-CDMA), modeling interference from users communicating with neighboring base stations by additive colored noise. We con...
200
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...