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» Optimizing for parallelism and data locality
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IPPS
2008
IEEE
16 years 1 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
ICDCS
2006
IEEE
16 years 22 days ago
Interplay of ISPs: Distributed Resource Allocation and Revenue Maximization
The Internet is a hierarchical architecture comprising heterogeneous entities of privately owned infrastructures, where higher level Internet service providers (ISPs) supply conne...
Sam C. M. Lee, Joe W. J. Jiang, John C. S. Lui, Da...
WMPI
2004
ACM
16 years 3 days ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
CORR
2010
Springer
91views Education» more  CORR 2010»
15 years 1 months ago
TSDS: high-performance merge, subset, and filter software for time series-like data
Time Series Data Server (TSDS) is a software package for implementing a server that provides fast supersetting, sub-setting, filtering, and uniform gridding of time series-like dat...
Robert S. Weigel, Doug M. Lindholm, A. Wilson, Jer...
GECCO
2006
Springer
186views Optimization» more  GECCO 2006»
15 years 10 months ago
Characterizing large text corpora using a maximum variation sampling genetic algorithm
An enormous amount of information available via the Internet exists. Much of this data is in the form of text-based documents. These documents cover a variety of topics that are v...
Robert M. Patton, Thomas E. Potok