1276 search results - page 121 / 256 » Optimizing Hierarchical Schedules for Improved Control Perfo... |
170
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ICASSP
2008
IEEE
16 years 27 days ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
205
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ICNP
2007
IEEE
16 years 23 days ago
2007
IEEE
Power conservation is a general concern for mobile computing and communication. In this paper, we investigate the performance of the current 802.11 power saving mechanism (unschedu...
170
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ICPADS
2006
IEEE
16 years 14 days ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
211
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SIGCOMM
2012
ACM
13 years 9 months ago
2012
ACM
Today’s data centers face extreme challenges in providing low latency. However, fair sharing, a principle commonly adopted in current congestion control protocols, is far from o...
200
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RTCSA
2003
IEEE
15 years 11 months ago
2003
IEEE
Network of workstation (NOW) is a cost-effective alternative to massively parallel supercomputers. As commercially available off-theshelf processors become cheaper and faster, it...