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FPL
2004
Springer
144views Hardware» more  FPL 2004»
15 years 10 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
SIGIR
2011
ACM
14 years 9 months ago
Fast context-aware recommendations with factorization machines
The situation in which a choice is made is an important information for recommender systems. Context-aware recommenders take this information into account to make predictions. So ...
Steffen Rendle, Zeno Gantner, Christoph Freudentha...
CIKM
2011
Springer
14 years 6 months ago
MTopS: scalable processing of continuous top-k multi-query workloads
A continuous top-k query retrieves the k most preferred objects in a data stream according to a given preference function. These queries are important for a broad spectrum of appl...
Avani Shastri, Di Yang, Elke A. Rundensteiner, Mat...
INFOCOM
2009
IEEE
16 years 1 months ago
Minimizing Delay for Multicast-Streaming in Wireless Networks with Network Coding
—Network coding is a method that promises to achieve the min-cut capacity in multicasts. However, pushing towards this gain in throughput comes with two sacrifices. Delay suffer...
Wai-Leong Yeow, Anh Tuan Hoang, Chen-Khong Tham
LCTRTS
2007
Springer
16 years 15 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...