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ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
16 years 2 days ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
16 years 23 hour ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
ISSS
1999
IEEE
109views Hardware» more  ISSS 1999»
15 years 12 months ago
Loop Alignment for Memory Accesses Optimization
Portable or embedded systems allow more and more complex applications like multimedia today. These applications and submicronic technologies have made the power consumption criter...
Antoine Fraboulet, Guillaume Huard, Anne Mignotte
TOOLS
1999
IEEE
15 years 12 months ago
Optimizing Object-Oriented Collection Join Queries through Path Traversals
Path traversals have been recognized as one of the strengths of object-oriented query processing as object retrieval can be carried out through pointer navigation. Apart from path...
David Taniar
GECCO
1999
Springer
133views Optimization» more  GECCO 1999»
15 years 12 months ago
Forecasting the MagnetoEncephaloGram (MEG) of Epileptic Patients Using Genetically Optimized Neural Networks
In this work MagnetoEncephaloGram (MEG) recordings of epileptic patients were analyzed using a hybrid neural networks training algorithm. This algorithm combines genetic algorithm...
Adam V. Adamopoulos, Efstratios F. Georgopoulos, S...