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3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
16 years 1 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner
ANSS
2006
IEEE
16 years 1 months ago
Modeling and Optimization for the Design of IMS Networks
The IP Multimedia Subsystem (IMS) is envisioned as the solution for the next generation multimedia rich communication. Based on an open IP infrastructure, it enables convergence o...
Nisha Rajagopal, Michael Devetsikiotis
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
16 years 1 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
DATE
2006
IEEE
66views Hardware» more  DATE 2006»
16 years 1 months ago
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 1 months ago
Optimizing sequential cycles through Shannon decomposition and retiming
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
Cristian Soviani, Olivier Tardieu, Stephen A. Edwa...