34170 search results - page 6236 / 6834 » Optimization |
208
click to vote
DAC
2009
ACM
16 years 8 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
194
click to vote
DAC
2008
ACM
16 years 8 months ago
2008
ACM
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
205
click to vote
DAC
2008
ACM
16 years 8 months ago
2008
ACM
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
209
click to vote
DAC
2007
ACM
16 years 8 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
228
click to vote
DAC
2007
ACM
16 years 8 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...