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ICCD
2008
IEEE
124views Hardware» more  ICCD 2008»
16 years 4 months ago
Global bus route optimization with application to microarchitectural design exploration
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
Dae Hyun Kim, Sung Kyu Lim
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
16 years 4 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch
ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
16 years 4 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
16 years 4 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...
IUI
2009
ACM
16 years 4 months ago
Searching large indexes on tiny devices: optimizing binary search with character pinning
The small physical size of mobile devices imposes dramatic restrictions on the user interface (UI). With the ever increasing capacity of these devices as well as access to large o...
Guy Shani, Christopher Meek, Tim Paek, Bo Thiesson...