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PASTE
2010
ACM
15 years 12 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
ASPLOS
1998
ACM
15 years 11 months ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
164
Voted
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 11 months ago
Coherent Network Interfaces for Fine-Grain Communication
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hil...
CASES
2008
ACM
15 years 9 months ago
Cache-aware cross-profiling for java processors
Performance evaluation of embedded software is essential in an early development phase so as to ensure that the software will run on the embedded device's limited computing r...
Walter Binder, Alex Villazón, Martin Schoeb...
190
Voted
ASPLOS
2006
ACM
15 years 9 months ago
Tradeoffs in fine-grained heap memory protection
Different uses of memory protection schemes have different needs in terms of granularity. For example, heap security can benefit from chunk separation (by using protected "pa...
Jianli Shen, Guru Venkataramani, Milos Prvulovic